Products by Design Area

Electronic System Level Design

System Integration

Visual Elite

System Debug

Vista

System Analysis

System Architect

High Level Synthesis

Catapult C Synthesis

Catapult Library Builder

Platform-Based Design

Platform Express Professional

Platform Express Integrator's Kit

Platform Express Client

Embedded Systems

Development Tools

EDGE Developer Suite

Operating System

Nucleus Kernel

Nucleus Networking

Nucleus Graphics and GUI

Nucleus File System

Nucleus USB

Nucleus Bus Support

Nucleus Security/Encryption

Application Platform

Inflexion Platform UI

Intellectual Property

USB

USB 2.0 OTG (On-The-Go)

USB 2.0 High/Full-Speed Function

Full-Speed USB 2.0 PHY

High-Speed USB 2.0 PHY

USB Software Stack

Ethernet

10/100 Platform

10/100/1000 Platform

10-Gigabit

PCI Express

PCIe 1.1 Controller Family

PCI to AMBA 2 AHB Bridge

PCI to AMBA 3 AXI Bridge

Storage

Serial ATA

Serial ATA 1.5/3.0 Gbps PHY

Parallel ATA

PCMCIA

Peripheral

Processor

IP Interface

Mixed Signal

Full-Speed USB 2.0 PHY

High-Speed USB 2.0 PHY

Serial ATA 1.5/3.0 Gbps PHY

IC Nanometer Design

Digital Design & Simulation

Custom Design & Simulation

Design Architect IC

ADiT

Eldo

Eldo RF

Mixed Signal Circuit Simulation

ADVance MS

ADVance MS RF

Block-Level Physical Design & Verification

Olympus-SoC

Pinnacle

Calibre nmDRC

Calibre nmLVS

Calibre xRC

Calibre xL

Calibre LFD: Litho-Friendly Design

Calibre YieldAnalyzer

Calibre YieldEnhancer

IC Station SDL

Calibre RVE

Calibre Interactive

Chip-Level Floorplan & Place & Route

Olympus-SoC

Pinnacle

Calibre DESIGNrev

IC Station SDL

Layout Verification

Olympus-SoC

Pinnacle

Calibre nmDRC

Calibre nmLVS

Calibre YieldAnalyzer

Calibre YieldEnhancer

Calibre RVE

Calibre Interactive

Full-Chip Parasitic Extraction

Calibre xRC

Calibre xL

Calibre RVE

Calibre Interactive

Mask Synthesis (RET & Mask Preparation)

Calibre nmOPC

Calibre OPCverify

Calibre LFD: Litho-Friendly Design

Calibre RET (OPC and PSM)

Calibre MDP

Calibre nmDRC

Chip Manufacturing & Test

Circuit Verification

Calibre xRC

Calibre nmLVS

Calibre xL

Calibre PERC

Scalable Verification

Verification Components

Assertion-Based Verification

Questa AFV (Advanced Functional Verification)

Questa SV (SystemVerilog)

0-In Formal Verification

0-In® Clock-Domain Crossing (CDC)

0-In® CheckerWare® Compiler

Testbench Creation & Automation

Questa AFV (Advanced Functional Verification)

Questa SV (SystemVerilog)

inFact (Intelligent Testbench Automation)

Questa Codelink

Coverage-Driven Verification

Questa AFV (Advanced Functional Verification)

Questa SV (SystemVerilog)

0-In® Assertion Synthesis

0-In Formal Verification

0-In® CheckerWare®

Equivalence Checking

FormalPro

Analog/Mixed-Signal Simulation

ADVance MS

ADVance MS RF

Hardware/Software Co-Verification

Seamless

Seamless FPGA

Hardware-Assisted Verification

Veloce

TestBench XPress (TBX)

iSolve Solutions

VStationPRO

Digital Simulation

ModelSim® SE

ModelSim® LE

ModelSim® PE

PCB Systems

System Design

DxDesigner

I/O Designer

Constraint Editor System

RF Design

Library Manager

Analysis & Verification

HyperLynx

HyperLynx Thermal

HyperLynx Analog

ICX / TAU

Quiet Expert

Physical Design

RF Design

Electro-Mechanical Collaboration

Data Management

Manufacturing

CAMCAD Professional

visECAD

CAMCAD Data Suite

CAMCAD Test Suite

eSight DFM

BOM Explorer

Data Exchange

CAMDOCS

Expedition Enterprise

System Design

DxDesigner

I/O Designer

Constraint Editor System

RF Design

Analysis & Verification

HyperLynx

HyperLynx Thermal

HyperLynx Analog

DxAnalog

ICX / TAU

Quiet Expert

Physical Design

Expedition PCB

Topology Router

TeamPCB

Xtreme Design

FabLink XE

Automation

Supermax ECAD

RF Design

Electro-Mechanical Collaboration

Flex Technology

Data Management

DMS

Library Manager

Manufacturing

FPGA/PLD

FPGA Advantage

Design Creation

HDL Designer

HDL Author

HDL Detective

Simulation

ModelSim® SE 

ModelSim PE

Synthesis

Precision RTL

Precision RTL Plus

Precision Physical

LeonardoSpectrum

Requirements Tracking

Design-For-Test (DFT)

ATPG & Compression

TestKompress

FastScan

DFTAdvisor

FlexTest

Memory Test

MBISTArchitect

MacroTest

Boundary Scan

BSDArchitect

Logic BIST

LBISTArchitect

Yield Learning and Diagnosis

YieldAssist

ATPG & Compression Video

Yield Learning and Diagnosis Video

System Modeling

System Integration, Simulation, and Analysis

SystemVision

BridgePoint UML Suite

BridgePoint Builder

BridgePoint Model Compiler

BridgePoint Verifier

Electrical System Design and Harness Engineering

Electrical Design

Capital Logic

Capital Integrator

Capital Ground Design

Simulation & Analysis

Capital SimTransient

Capital SimScript

Capital SimStress

Capital SimProve

Capital SimCertify

Design Data Management

Capital Manager

Engineering & Manufacturing

Capital HarnessXC

Capital Engineer

Capital Modular

Capital Labor & Material Cost Analyzer

Capital Factory - Bridges

Capital Harness - OEM Modules

Capital FormboardXC

Enterprise Integration

Capital Autoloader

Capital Integration Server

Bridges for CHS

Logical Systems Capture

Capital Capture

VeSys Design

VeSys Harness

VeSys Service

VeSys Components

Views and Documentation

Capital AVAssist Integrator

Capital AVAssist Logic

Capital AVAssist Blocks

Capital AVAssist Filtering