Technical Publications
Hardware/Software Validation with a TLM Virtual System Prototype
With all the complexity associated with the hardware, the software is also crucial to the competitive success of these products. The application software often is the key differentiator for these consumer products, allowing the system company to reap substantial profit margins. Software is also key in the power and performance behavior of the hardware platform.
Using High-Level Synthesis for FPGA Development
Designing High Performance DSP Hardware using Catapult C Synthesis and the Altera Accelerated Libraries
Today's class of high-performance FPGAs such as the Altera Stratix III provide design engineers with a hardware platform that is capable of addressing the computational requirements needed to implement many of the next-generation wireless and video algorithms. Although these devices provide dedicated hardware to implement the basic building blocks of digital signal processing (DSP) algorithms such as multiply-accumulate (MAC), designers still must meet the challenges of rapidly taking an algorithm from concept to implementation in RTL.
Historically, the design flow consisted of modeling the algorithm functionality in a high-level language such as C++ and then hand-coding it in RTL. This manual method of RTL creation is not only time consuming and error prone, but often is highly sensitive to back-end routing delay problems. Catapult High-level C++ synthesis has historically been used to build ASIC hardware sub-systems found in extremely complex and compute intensive applications found in wireless, video and image processing. Combining Catapult's ASIC capabilities with Altera Accelerated Libraries provides designers with a rapid path from algorithms modeled in ANSI C++ to optimized RTL running in FPGA hardware. Furthermore, this design flow allows designers to directly target the FPGA DSP blocks from C++, easily solving back-end timing problems using high-level synthesis constraints.
Requirements for a True Mixed-Level TLM-RTL Design Environment
Today's incredibly large and complex digital ICs (ASICs, ASSPs, and SoCs) can easily contain tens of millions of logic gates. The only realistic way to create and verify designs of this size and complexity is to use a mixture of pre-defined intellectual property (IP) blocks and application-specific logic.
In this case, the pre-defined IP blocks - which may be internally developed, but which are often acquired from third-party vendors - are used to implement well-known functions such as general-purpose microprocessor cores, special-purpose digital signal processor cores, peripheral functions, memory interfaces, and high-speed data interfaces. This leaves the designers free to focus their time and resources on the application-specific ("secret sauce") logic that will differentiate this product from any competitor offerings.
Utilizing SystemC for Design and Verification
The number one reason for the use of SystemC is the significantly increased simulation performance at the TLM level over executable platforms modeled at the RT level using Verilog or VHDL. SystemC TL models are fast enough to serve as a software development platform allowing for early software development and for co-simulation of hardware and software. Both TL and functional models are fast enough for system level architectural modeling and analysis.
The second reason for SystemC use is functional verification. The same executable platform that is used to develop the software is often used for verification of the entire system. This verification occurs early on in a project and the TLM becomes a golden reference for the entire system. Because SystemC is C++, it has a number of inherent properties, such as classes, templates and inheritance, that lend themselves to verification. These capabilities are extended with the SystemC Verification Library (discussed later) making SystemC a powerful verification language as well as modeling language.
This exhaustive examination includes dozens of graphics, a glossary and code appendix.
Creating a Consistent Verification Environment from Algorithm to RTL
An ESL Methodology for Functional Verification between Untimed C++ and RTL using SystemC
System-level Validation Increases Design Productivity and Saves Errors
Using a Catapult C-Based flow to Speed Implementation and Increase Flexibility
Toshiba creates Eigenvalue Decomposition using Catapult C Synthesis
This report written by Toshiba Information Systems discusses the hardware implementation of "eigenvalue decomposition". Eigenvalue decomposition is used in a wide range of applications for imaging, communication and audio such as image recognition using KL conversion, high-speed communication using MIMO antenna, and electric/sound wave arrival direction estimation using MUSIC method. It is expected that more than four antennas will be required in many cases for future MIMO communications and electric wave arrival direction estimation with MUSIC method applications. Here we were interested in verifying whether the method to obtain eigenvalues directly from the eigenvalue equation was reasonable or not. Therefore, we developed two effective algorithms in ANSI C++ to obtain eigenvalues and synthesized them with Catapult C Synthesis to compare the area versus the number of cycles at the algorithm level, respectively.
New Catapult C Design Flow is an Unqualified Success
Dennis McCain, Research Manager at Nokia Research Center states, "When we started evaluating Catapult C, we quickly realized that we had found a winning solution. However, we had no conception that we?d move from using this tool in a beta site evaluation role to using it for mission-critical portions of our design so quickly."
This case study explains why Nokia's evaluations were so successful that CatapultTM C Synthesis ended up being used for the mission-critical portions of the design.