Creating Web-based Repositories for Reuse
Overview
Technology, Reuse and HDL Design: Approaches for ASIC or FPGA Designers
To meet the schedules and demands for complex ASIC and FPGA design projects, reusing HDL code as building blocks for new and next generation designs has become a common practice. Since a large volume of code from many designers and projects often exists within a company, the reuse approach seems very practical, but in reality, the reuse task can prove to be very challenging. Join us for these thirty minute online seminars to learn some practical approaches to design projects, managing the files and artifacts and incorporating methods to improve efficiency and design reuse. The demonstrations are especially useful for engineers that use or are familiar with HDL Designer Series.
Times:
- Asia Pacific – 13:00 Tokyo
- Europe & North America – 15:00 London, 10:00am New York
- North America – 2:00pm San Francisco
Who Should Attend
- Engineering managers
- Project managers
- Engineers and designers
What You Will Learn
Once the design team has created a design, how can they easily reuse and share it through out the company? This presentation will show how HDL Designer tool features can greatly simplify this process. As part of this session, a short demonstration will illustrate how HDL Designer allows the design team to populate a design repository without a lot of infrastructure requirements.