Technical Publications
Improving FPGA Prototyping with SystemVerilog
As ASIC designs have grown larger at a much faster pace than FPGA devices, often multiple FPGA devices must be used to prototype a single ASIC. The obstacle of using multiple devices is the task of connecting all of the logical blocks of the ASIC design across multiple FPGA devices. However, methods for logically connecting the design blocks have proven to be manually intensive and error prone. With the introduction of SystemVerilog, an evolutionary RTL language, and advanced mixed language synthesis tools such as Mentor Graphics' Precision Synthesis, the procedure for connection has been simplified.
FPGA Synthesis: Looking Beyond the Obvious
In many cases, design requirements refer to performance and area—the design needs to operate at a minimum frequency and naturally needs to fit into the selected device. Hence, designers or CAD managers looking to standardize on a synthesis flow tend to look for good out-of-the-box quality-of-results (QoR).
Often, to meet aggressive QoR goals, constraints need to be refined, optimizations must be enabled, or small portions of RTL may need to be re-coded—but without help from the tool it is difficult to identify when and where to make these changes. In other cases QoR goals may have been met but design changes are constantly being introduced, and new changes either degrade previous QoR results or runtime for each change delays project schedule. FPGA project managers must take into account these scenarios and consider how their synthesis flow addresses them.
DO-254 Compliance: Reducing Project Cost by Avoiding Common Pitfalls
Many folks stumble on very similar issues when they begin their journey towards creating and executing DO-254 compliant design projects. The good news is that each of these issues has solutions. Understanding these common pitfalls, and proactively addressing them before they cost a project time, resource and certification risk, is essential. Some of these common pitfalls, along with advice for addressing them (based on learnings from successful DO-254 programs), are described in this paper.
Raising the RTL Abstraction Level and Design Conciseness with SystemVerilog
With the advent of advanced HDLs that provide new and powerful language constructs, such as SystemVerilog, hardware modeling styles can now be enhanced both in terms of abstraction levels and overall efficiency. Developing concise, accurate designs entails learning how SystemVerilog features can be effectively used to design efficient and synthesizable models for both ASICs and FPGAs.
This paper will focus on the impact of new extensions and constructs in SystemVerilog on hardware designs and describe the usefulness and compatibility of these constructs vis-à-vis pure Verilog constructs
Implementing SystemVerilog for FPGA Design
Managing Timing Constraints with Precision Synthesis
Preserving Freedom of Choice When Designing FPGAs
The Use of Advanced Verification Methods to Address DO-254 Design Assurance
Achieving Quality and Traceability in FPGA/ASIC Flows for DO-254 Aviation Projects
With the recent FAA/EASA mandate, companies providing flight hardware for commercial aviation systems now must build their complex electronic hardware components (i.e., ASIC/FPGA) to the standard known as DO-254. Focusing on design assurance (including quality, traceability, and strict configuration management), the DO-254 standard can have a profound impact on a company's development processes and design flows.
This paper discusses the application of advanced methodologies and integrated tool flows for ASIC/FPGA design and verification, showing how to implement a high quality flow that provides the required assurance while maintaining cost and schedules.