SV Technical Publications

This document provides an overview of sequences and shows all the code necessary to use sequences within the OVM.

The Open Verification Methodology (OVM) provides a framework that includes both a methodology and code libraries that a verification engineer can use to build a testbench that is modular, interoperable, and reusable. The inFact® intelligent testbench automation tool allows the user to build testbench components whose activity is controlled by one or more rule graphs that define the verification scenarios and stimuli that are to be applied to the device under verification (DUV) or to one of its interfaces.

This application note describes how you would construct an inFact OVM component and include it within an OVM-based testbench. It is assumed that the user is already familiar with other aspects of the inFact tool, such as building the rule graphs, coverage objects etc. It is also assumed that the user has a good understanding of the OVM.

With the recent FAA/EASA mandate, companies providing flight hardware for commercial aviation systems now must build their complex electronic hardware components (i.e., ASIC/FPGA) to the standard known as DO-254. Focusing on design assurance (including quality, traceability, and strict configuration management), the DO-254 standard can have a profound impact on a company's development processes and design flows.

This paper discusses the application of advanced methodologies and integrated tool flows for ASIC/FPGA design and verification, showing how to implement a high quality flow that provides the required assurance while maintaining cost and schedules.

As designs get more complex and previously independent functions become integrated on a single chip, chips with multiple asynchronous clock domains are becoming the norm. Signals that cross between these domains called clock-domain crossings, or simply "CDCs") can result in metastable operation, which often causes intermittent chip failures that can go undetected until the chip is in the lab or even operating in the field. This is a serious risk to safe system operation (not to mention the long debug times and extensive costs associated with troubleshooting and fixing these difficult problems). This concern is driving a swift adoption of CDC verification tools even into military and aerospace companies.

This paper introduces the issues concerning CDC, how to verify CDCs to avoid inadvertent design failures, and how/why to use 0-In CDC on DO-254 projects (including what is needed for tool assessment).

Existing testbench techniques offer various benefits. However, once a testbench is initiated, it runs open-loop, generating results and then reporting them to an engineer. In turn, the engineer analyzes the results, makes some modifications to the system, and runs it again - and then repeats the process. The process runs open-loop, requires human intervention, and the iterations can span weeks, or even months.

Most verification engineers consider the "learning testbench" to be a vision of the future. However, a new advanced closed-loop testbench automation system "learns" from both the DUT and the testbench modules during simulations. By combining concepts previously associated with compiler test automation and logic design synthesis, along with some innovative recently-patented technology, Mentor Graphics augments directed testing and constrained random testing with intelligent testing - a learning-based system that actively targets desired results, rather than merely reporting them.