SV Technical Publications
Binding SystemVerilog to VHDL Components Using Questa
Binding SystemVerilog to VHDL Components Using Questa SystemVerilog offers a rich set of testbench automation capabilities, native assertions, and functional coverage. These features make SystemVerilog increasingly appealing to VHDL users who need to implement an efficient and effective functional verification methodology.
The Questa(tm) advanced verification environment offers native support of SystemVerilog, Verilog, and VHDL, making it easy to adopt SystemVerilog.
The flexibility provided by Questa's single kernel architecture enables VHDL users to easily attach SystemVerilog to existing VHDL components. The connection is made using the SystemVerilog bind function, which gives modules and program blocks access to both external ports and internal signals in the bound VHDL object. Among other things, you can use this capability to monitor VHDL functionality with SystemVerilog Assertions (SVA) or assess the functional coverage of VHDL designs.
The Use of Advanced Verification Methods to Address DO-254 Design Assurance
Achieving Quality and Traceability in FPGA/ASIC Flows for DO-254 Aviation Projects
With the recent FAA/EASA mandate, companies providing flight hardware for commercial aviation systems now must build their complex electronic hardware components (i.e., ASIC/FPGA) to the standard known as DO-254. Focusing on design assurance (including quality, traceability, and strict configuration management), the DO-254 standard can have a profound impact on a company's development processes and design flows.
This paper discusses the application of advanced methodologies and integrated tool flows for ASIC/FPGA design and verification, showing how to implement a high quality flow that provides the required assurance while maintaining cost and schedules.
Automating Clock-Domain Crossing Verification for Do-254 (and other Safety-Critical) Designs
As designs get more complex and previously independent functions become integrated on a single chip, chips with multiple asynchronous clock domains are becoming the norm. Signals that cross between these domains called clock-domain crossings, or simply "CDCs") can result in metastable operation, which often causes intermittent chip failures that can go undetected until the chip is in the lab or even operating in the field. This is a serious risk to safe system operation (not to mention the long debug times and extensive costs associated with troubleshooting and fixing these difficult problems). This concern is driving a swift adoption of CDC verification tools even into military and aerospace companies.
This paper introduces the issues concerning CDC, how to verify CDCs to avoid inadvertent design failures, and how/why to use 0-In CDC on DO-254 projects (including what is needed for tool assessment).
A Comparison of Metastability Modeling Methods
Low Power Design and Verification Techniques
Effective Functional Verification Methodologies for DO-254 Level A/B and Other Safety-Critical Devices
Planning Formal Verification Closure
DO-254: Understanding the Issues that Impact Business
SVA Local Variable Coding Guidelines for Efficient Use
The expressive power of SystemVerilog assertions (SVA) with local variables enables you to specify complex properties in a concise form (for example, properties involving data integrity). However, using local variables might result in unacceptable performance during simulation or formal verification if you do not take precautions when coding your assertions.
This paper provides a set of coding guidelines and a methodology for efficient SVAlocal variable use. Our guidelines allow you to take advantage of the expressiveness of SVAlocal variables while avoiding potential pitfalls that can result in reduced performance and capacity.